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AI-agent MCP server for FPGA design: compile, validate & generate Verilog from C⏚ HDL.
This server publishes no hosted endpoint. Run one of its packages locally.
neosyn-fpga-mcp · pypi 1.4.0 · stdio
claude mcp add --transport stdio neosyn-fpga-mcp -- uvx neosyn-fpga-mcp==1.4.0